1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of holding storage data without a refresh operation.
2. Description of the Background Art
In a semiconductor memory device, in particular in an SRAM (Static Random Access Memory), power consumption can be lowered by controlling a source potential of a transistor constituting a memory cell so as to suppress a leakage current that flows between the source and the drain, for example.
A conventional semiconductor memory device (a semiconductor device) disclosed in Japanese Patent Laying-Open No. 9-73784 reduces the leakage current by maintaining a reading speed by setting the source potential equal to a substrate potential during an operation, and by setting an absolute potential of the source to be higher than the substrate potential during waiting. Though the conventional semiconductor memory device disclosed in waiting, it does not reduce the leakage current during the operation. Therefore, lowering of power consumption during the operation is not expected.
Generally, power consumed during operation of the semiconductor memory device is the sum of power consumption by charging/discharging current of a bit line or the like and power consumption by the leakage current. Though the charging/discharging current of the bit line or the like has accounted for a large part of the power consumption so far, power consumption by the leakage current during operation is not negligible when the threshold value is set lower in accordance with the higher speed of the semiconductor memory device.
A conventional semiconductor memory device (a semiconductor integrated circuit) disclosed in Japanese Patent Laying-Open No. 2002-288984 reduces the leakage current by setting the source potential of a selected memory cell row to be equal to the substrate potential and by setting the absolute potential of the source of a non-selected memory cell row to be higher than the substrate potential during a reading operation. The conventional semiconductor memory device disclosed in Japanese Patent Laying-Open No. 2002-288984 can suppress the leakage current in memory cells other than the selected memory cell even during the operation. For example, in the case of a semiconductor memory device including a memory cell array of 512 rows and 512 columns, 512 memory cells, that are equivalent to one row, are selected, and hence an increase of the overall leakage current is suppressed to 1/512.
As described above, the conventional semiconductor memory devices disclosed in the references above have lowered power consumption by controlling the source potential so as to suppress the leakage current that flows between the source and the drain. On the other hand, these semiconductor memory devices cannot reduce power consumption by the charging/discharging current of the bit line or the like, which is one factor of the power consumption during operation.
In addition, with regard to the conventional semiconductor memory devices disclosed in the references above, only an example of a single-port memory cell constituted of 6 transistors has been shown, and lower power consumption in an example of a multi-port memory cell including a bit line dedicated for reading has not been shown.
Moreover, with regard to the conventional semiconductor memory devices disclosed in the references above, the leakage current between the source and the drain in a transistor that has turned off is solely considered. Namely, an influence of the gate leakage current, which has become apparent as a gate insulating film is made thinner, has not been addressed.